So you are simulating a verilog design with Verilator and you want to output part of your design data to a file in binary format. (Example you’re outputting an image.)
Tag Archive for 'verilog'
I sent an email to the fx2lib mailing list that I thought would make good information for a bigger audience. Eventually, I’ll probably provide a Verilog behavioral model for the GPIF on the Cy7C68013 (and variants), but for now, this may help a few of you: Rdy0,1, txpire etc, are registered (The data 7:0 is […]