I sent an email to the fx2lib mailing list that I thought would make good information for a bigger audience. Eventually, I'll probably provide a Verilog behavioral model for the GPIF on the Cy7C68013 (and variants), but for now, this may help a few of you:
- Rdy0,1, txpire etc, are registered (The data 7:0 is too). That means if Rdy0, rdy1 are true when the decision point tests them, that they were actually set during the previous clock cycle.
- When you enter a state, any control lines you set are registered out. That means if you set ctl0 high on state 2, that whatever you connect to the gpif receives the high a clock cycle later.
I started to develop a behavioral model for this. It goes something like this if you are familiar with Verilog:
- reg [2:0] state;
- reg rdy0_r, rdy1_r;
- reg ctl0_r,ctl1_r,ctl2_r;
- reg data_r[7:0];
- always @(posedge clk) begin
- rdy0_r <= // rdy0 signal
- rdy1_r <= // rdy1 signal
- data_r <= // data signals
- case (state)
- ctl0_r <= // state 0 ctl0 state
- // example decision point logic
- if (rdy0_r) begin
- state <= STATE1;
- ctl2_r <= // whatever you set the control lines to in state 1.
- // example read state // do something with data
- someoutput <= data_r; // whatever
- if ( !rdy0_r) begin // decision point logic
- state <= STATE2;
- // etc... I don't yet have code to dynamically read the gpif output
- // so until then, I just coded each state the same as I did in the
- // gpif designer.
Anyway, I was able to get a functioning simulation of my device from the perspective of the 8051 by modeling the GPIF this way. When I get some time, I'd like to make this generic enough to parse the GPIF designer output and model each state dynamically so the simulation can simply call the single read, single write, and fifo waveforms and the model will execute the waveform correctly. For now, if you're going down this road of simulation, you should be able to simply mimic your GPIF waveform this way.