Tag Archives: verilog

Writing binary data with Verilator

So you are simulating a verilog design with Verilator and you want to output part of your design data to a file in binary format. (Example you’re outputting an image.) Continue reading

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Cypress GPIF waveform behavioral model

I sent an email to the fx2lib mailing list that I thought would make good information for a bigger audience. Eventually, I’ll probably provide a Verilog behavioral model for the GPIF on the Cy7C68013 (and variants), but for now, this … Continue reading

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