I’ve been optimizing my firmware for throughput and I thought a good benchmark would be to test it against the CyStream example provided by Cypress. I modified their CyStream.c file to be compatible with the latest firmware file provided by fx2lib.
Here is a summary of the changes needed:
- Include the appropriate header files
- Change the functions for vendor commands to match the fx2lib functions.
- Change the interrupt handlers
- Probably the most work of the whole process, rewrite the dscr.a51 file to be in asx8051 format.
Anyhow, The attached zip files contains the sources for the modified CyStream. Here are some of my benchmark results:
|CyStream Application on Windows with Keil firmware
|Keil firmware, Linux Host with included speed.py
|SDCC firmware, unchanged, speed.py
|SDCC firmware, optimization 1, speed.py
|SDCC firmware, optimization 2, speed.py
|SDCC firmware, optimization 3, speed,py
|SDCC firmware, optimization 3, CyStream App on Windows
- Optimization: remove two if checks for interrupts in main loop and handle them directly in the interrupts
- Optimization: remove another if in main loop.
- Optimization: completely remove everything in main loop, commit packets directly in main loop, don’t write to ep buffer before committing data. Note that the fastest I could get this to go was 42.9 (or 43.8 on Windows). Further removing things didn’t make it go any faster so I think I hit my Host PC limits.
You’ll need to download fetch the latest fx2lib from github and then modify the Makefile to compile the attached firmware. You’ll need to install the fx2load package for Python from fx2lib in order to run the speed test.
CyStream for SDCC and fx2lib
Enjoy. I hope fx2lib helps someone out. Check out my other posts on fx2lib to find our mailing list and more SDCC examples for the Cypress FX2.
I sent an email to the fx2lib mailing list that I thought would make good information for a bigger audience. Eventually, I’ll probably provide a Verilog behavioral model for the GPIF on the Cy7C68013 (and variants), but for now, this may help a few of you:
- Rdy0,1, txpire etc, are registered (The data 7:0 is too). That means if Rdy0, rdy1 are true when the decision point tests them, that they were actually set during the previous clock cycle.
- When you enter a state, any control lines you set are registered out. That means if you set ctl0 high on state 2, that whatever you connect to the gpif receives the high a clock cycle later.
I started to develop a behavioral model for this. It goes something like this if you are familiar with Verilog:
reg [2:0] state;
reg rdy0_r, rdy1_r;
always @(posedge clk) begin
rdy0_r <= // rdy0 signal
rdy1_r <= // rdy1 signal
data_r <= // data signals
ctl0_r <= // state 0 ctl0 state
// example decision point logic
if (rdy0_r) begin
state <= STATE1;
ctl2_r <= // whatever you set the control lines to in state 1.
// example read state // do something with data
someoutput <= data_r; // whatever
if ( !rdy0_r) begin // decision point logic
state <= STATE2;
// etc... I don't yet have code to dynamically read the gpif output
// so until then, I just coded each state the same as I did in the
// gpif designer.
Anyway, I was able to get a functioning simulation of my device from the perspective of the 8051 by modeling the GPIF this way. When I get some time, I'd like to make this generic enough to parse the GPIF designer output and model each state dynamically so the simulation can simply call the single read, single write, and fifo waveforms and the model will execute the waveform correctly. For now, if you're going down this road of simulation, you should be able to simply mimic your GPIF waveform this way.
I’ve uploaded documentation and a source download for fx2lib. Here is the copy of the Sourceforge announcement.
The fx2lib sources are stable enough to build complete firmware implementations for the cypress fx/fx2 variants of the 8051 chipset.
The current release includes library functions for:
- delay functions
- endpoint functions
- register definitions
- type definitions
- macros for common tasks
- GPIF functions
- i2c functions
- serial IO
- USB jump tables
- vendor commands and setup data.
Library documentation is located at: http://fx2lib.sourceforge.net/docs/
Sources can be downloaded from the project download page: https://sourceforge.net/project/showfiles.php?group_id=247216
Development on fx2lib occurs in a git repository at: http://github.com/mulicheng/fx2lib/
Check out my other posts on fx2 programming for reference. If you are interested, there is much information to discuss on the fx2lib mailing list too. Check the fx2lib home page for information on joining the list.
After playing around with the Cypress FX2 and SDCC for the past while, I’ve developed a library of utilities that make some of the common tasks for writing firmware and performing certain functions a little easier. I’m lucky to work for a company that approves of the open source initiative and believes that it is beneficial to give back as well as receive from a wider audience of developers. That being said, I’ve created a git repository with my library:
Here is fx2lib on github: http://github.com/mulicheng/fx2lib/
You can clone it with git like this:
> git clone git://github.com/mulicheng/fx2lib.git fx2lib
Here is a short list of some of the things you can do with this library:
- Read/Write data on the i2c bus
- Handle USB and GPIF interrupts
- Read/Write data on to a serial console
- Handle the common USB vendor commands
- Implement your own vendor commands
- Program the GPIF
Hope you enjoy!
Update 12/15/08: Added project home page at Sourceforge: fx2lib home.